Google Tensor Processing Unit / variant
Eighth-gen training chip; Broadcom-led architecture on TSMC N2; 2 compute dies + 1 I/O chiplet + 8 stacks of 12-high HBM3e (≈30% more BW than v7p) [1]. MediaTek contributes I/O Die + back-end design service per 工商時報 2026-04-27, with that portion on TSMC N3P + CoWoS-S [3].
區間 + 信心水準 + 來源；不同分析師、不同時點的預估會並列。
| 期間 | 出貨量 (low–mid–high) | ASP (USD) | 信心 | 來源 |
|---|---|---|---|---|
| 2027 H2 | 200k–500k–800k | 0.02M | low | TheNextWeb 2026-04-22 + 工商時報 2026-04-27 |
| 2028 FY | 5000k–7000k–9000k | 0.02M | low | TheNextWeb 2026-04-22 four-partner report |
每行 = 單一機台的零組件 slot。share % 是該供應商在此 component 的估計份額。
GPU / CPU dies — the headline silicon.
Broadcom-led architecture; TSMC N2; 2 compute dies + 1 I/O chiplet.
MediaTek-designed I/O + back-end services; TSMC N3P.
HBM stacks attached to the compute die.
8 stacks × 12-high; ≈30% more BW than v7p.
Advanced packaging (CoWoS-L) + ABF substrate.
TSMC advanced packaging; competing with Intel EMIB long-term.
NICs, switches, cables, CPO modules.
Inter-chip interconnect for superpod scale-out.
