Google Tensor Processing Unit / variant
Eighth-gen inference chip; MediaTek-led on TSMC N2; 1 compute die + 1 I/O die + 6 stacks of HBM3e; targets 20–30% lower inference cost than 8t [1]. Previously referenced as v8e in pre-Cloud Next coverage.
區間 + 信心水準 + 來源；不同分析師、不同時點的預估會並列。
| 期間 | 出貨量 (low–mid–high) | ASP (USD) | 信心 | 來源 |
|---|---|---|---|---|
| 2027 H2 | 500k–1500k–2500k | 0.01M | low | TheNextWeb 2026-04-22 + Trendforce 2025-12-15 |
每行 = 單一機台的零組件 slot。share % 是該供應商在此 component 的估計份額。
GPU / CPU dies — the headline silicon.
MediaTek-led; TSMC N2; 1 compute die + 1 I/O die.
HBM stacks attached to the compute die.
6 stacks per chip.
Advanced packaging (CoWoS-L) + ABF substrate.
Final packaging TBD between TSMC CoWoS-S and Intel EMIB.
